Priority is claimed to Japanese Patent Application Number JP2004-089495 filed on Mar. 25, 2004, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a hybrid integrated circuit device. In particular, the present invention relates to a hybrid integrated circuit device having leads led to the outside.
2. Description of the Related Art
With reference to FIGS. 6A and 6B, the constitution of a conventional hybrid integrated circuit device 100 will be described. FIG. 6A is a plan view of the conventional hybrid integrated circuit device 100, and FIG. 6B is a cross-sectional view showing a packaging structure thereof.
Referring to FIG. 6A, a conductive pattern 102 is formed on the front surface of a circuit board 101 made of metal such as aluminum with an insulating layer interposed therebetween, and a desired hybrid integrated circuit device is realized by mounting circuit elements 105 at predetermined positions on the conductive pattern 102. Here, an IC, a chip resistor, a chip capacitor, a power transistor, and the like are adopted as the circuit elements 105, and a transistor mounted face-up is electrically connected to the conductive pattern 102 through fine metal wires 103. A plurality of pads 102A of the conductive pattern 102 are formed on one side edge of the circuit board 101. At the positions of the pads 102A, leads 104 are fixed with brazing material such as solder.
Referring to FIG. 6B, the hybrid integrated circuit device 100 is fixed to a mount board 111 by inserting the leads 104 into holes made in the mount board 111, thus establishing electrical connection. Further, in order to prevent the leads 104 from bending due to vibration or the like, the leads 104 have curved shapes.
With reference to FIG. 7, one example of a circuit formed in the hybrid integrated circuit device 100 will be described. FIG. 7 is a conceptual diagram showing the outline of a circuit formed on the front surface of the circuit board 101.
Here, a plurality of channels CH, each of which is an amplifier circuit for amplifying a signal inputted from one lead 104 and outputting the amplified signal from one lead 104, are formed on the front surface of the circuit board 101. Three channels each having such a circuit configuration are constituted.
A first channel CH1 is formed in the vicinity of a middle portion of the circuit board 101. A second channel CH2 is formed to surround the first channel CH1. A third channel CH3 is formed to surround the second channel CH2. This technology is described for instance in Japanese Patent Publication No. 2000-12987 (page 4, FIG. 1).
However, in the hybrid integrated circuit device 100, since the leads 104 are long, parasitic inductance are generated. This destabilizes the operation of the entire device. Further, the entire device is vertically fixed to a mount board in an upright position. This inhibits the thinning of a set in which the hybrid integrated circuit device is incorporated.
Moreover, if a plurality of channels are formed on the circuit board 101 in the case where the leads 104 are fixed on one edge of the circuit board 101, the length of each channel becomes uneven, and there has been the fear of problems such as electrical signal delay. Further, in order to equalize the length of each channel, means for crossing interconnections using jumper wires or the like are necessary. There has been the fear that this may newly increase the number of manufacturing steps and generate inductance sources.
Furthermore, there are cases where the voltages of input signals inputted into the hybrid integrated circuit device and those of output signals outputted from the hybrid integrated circuit device are greatly different from each other. In such a case, if a lead through which an input signal passes and a lead through which an output signal passes are adjacent to each other, there has been the problem that either of these signals is affected by the other.